SmartGlove_STM32H750VBTx_1.1.0.dbgconf 4.0 KB

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  1. // File: STM32H742_743_753_750.dbgconf
  2. // Version: 1.0.0
  3. // Note: refer to STM32H742, STM32H743/753 and STM32H750 reference manual (RM0433)
  4. // refer to STM32H742xI/G STM32H743xI/G datasheets
  5. // refer to STM32H753xI datasheet
  6. // refer to STM32H750VB STM32H750IB STM32H750XB datasheets
  7. // <<< Use Configuration Wizard in Context Menu >>>
  8. // <h> DBGMCU configuration register (DBGMCU_CR)
  9. // <o.28> TRGOEN <i> External trigger output enable
  10. // <o.8> DBGSTBY_D3 <i> Allow debug in D3 Standby mode
  11. // <o.7> DBGSTOP_D3 <i> Allow debug in D3 Stop mode
  12. // <o.2> DBGSTBY_D1 <i> Allow D1 domain debug in Standby mode
  13. // <o.1> DBGSTOP_D1 <i> Allow D1 domain debug in Stop mode
  14. // <o.0> DBGSLEEP_D1 <i> Allow D1 domain debug in Sleep mode
  15. // </h>
  16. DbgMCU_CR = 0x00000007;
  17. // <h> DBGMCU APB3 peripheral freeze register (DBGMCU_APB3FZ1)
  18. // <i> Reserved bits must be kept at reset value
  19. // <o.6> WWDG1 <i> WWDG1 stop in debug
  20. // </h>
  21. DbgMCU_APB3_Fz1 = 0x00000000;
  22. // <h> DBGMCU APB1L peripheral freeze register (DBGMCU_APB1LFZ1)
  23. // <i> Reserved bits must be kept at reset value
  24. // <o.23> DBG_I2C3 <i> I2C3 SMBUS timeout stop in debug
  25. // <o.22> DBG_I2C2 <i> I2C2 SMBUS timeout stop in debug
  26. // <o.21> DBG_I2C1 <i> I2C1 SMBUS timeout stop in debug
  27. // <o.9> DBG_LPTIM1 <i> LPTIM1 stop in debug
  28. // <o.8> DBG_TIM14 <i> TIM14 stop in debug
  29. // <o.7> DBG_TIM13 <i> TIM13 stop in debug
  30. // <o.6> DBG_TIM12 <i> TIM12 stop in debug
  31. // <o.5> DBG_TIM7 <i> TIM7 stop in debug
  32. // <o.4> DBG_TIM6 <i> TIM6 stop in debug
  33. // <o.3> DBG_TIM5 <i> TIM5 stop in debug
  34. // <o.2> DBG_TIM4 <i> TIM4 stop in debug
  35. // <o.1> DBG_TIM3 <i> TIM3 stop in debug
  36. // <o.0> DBG_TIM2 <i> TIM2 stop in debug
  37. // </h>
  38. DbgMCU_APB1L_Fz1 = 0x00000000;
  39. // <h> DBGMCU APB2 peripheral freeze register (DBGMCU_APB2FZ1)
  40. // <i> Reserved bits must be kept at reset value
  41. // <o.29> DBG_HRTIM <i> HRTIM stop in debug
  42. // <o.18> DBG_TIM17 <i> TIM17 stop in debug
  43. // <o.17> DBG_TIM16 <i> TIM16 stop in debug
  44. // <o.16> DBG_TIM15 <i> TIM15 stop in debug
  45. // <o.1> DBG_TIM8 <i> TIM8 stop in debug
  46. // <o.0> DBG_TIM1 <i> TIM1 stop in debug
  47. // </h>
  48. DbgMCU_APB2_Fz1 = 0x00000000;
  49. // <h> DBGMCU APB4 peripheral freeze register (DBGMCU_APB4FZ1)
  50. // <i> Reserved bits must be kept at reset value
  51. // <o.18> DBG_IIWDG1 <i> Independent watchdog for D1 stop in debug
  52. // <o.16> DBG_RTC <i> RTC stop in debug
  53. // <o.12> DBG_LPTIM5 <i> LPTIM5 stop in debug
  54. // <o.11> DBG_LPTIM4 <i> LPTIM4 stop in debug
  55. // <o.10> DBG_LPTIM3 <i> LPTIM2 stop in debug
  56. // <o.9> DBG_LPTIM2 <i> LPTIM2 stop in debug
  57. // <o.7> DBG_I2C4 <i> I2C4 SMBUS timeout stop in debug
  58. // </h>
  59. DbgMCU_APB4_Fz1 = 0x00000000;
  60. // <h> TPIU Pin Routing (TRACECLK fixed on Pin PE2)
  61. // <i> TRACECLK: Pin PE2
  62. // <o1> TRACED0
  63. // <i> ETM Trace Data 0
  64. // <0x00040003=> Pin PE3
  65. // <0x00020001=> Pin PC1
  66. // <0x0006000D=> Pin PG13
  67. // <o2> TRACED1
  68. // <i> ETM Trace Data 1
  69. // <0x00040004=> Pin PE4
  70. // <0x00020008=> Pin PC8
  71. // <0x0006000E=> Pin PG14
  72. // <o3> TRACED2
  73. // <i> ETM Trace Data 2
  74. // <0x00040005=> Pin PE5
  75. // <0x00030002=> Pin PD2
  76. // <o4> TRACED3
  77. // <i> ETM Trace Data 3
  78. // <0x00040006=> Pin PE6
  79. // <0x0002000C=> Pin PC12
  80. // </h>
  81. TraceClk_Pin = 0x00040002;
  82. TraceD0_Pin = 0x00040003;
  83. TraceD1_Pin = 0x00040004;
  84. TraceD2_Pin = 0x00040005;
  85. TraceD3_Pin = 0x00040006;
  86. // <<< end of configuration section >>>